CS-12 Computer ArchitectureDec-2000
Question Paper of CS-12 Computer ArchitectureDec-2000
Q.I (i) Consider a catch (M1,) and memory (M2:) hierarchy with the following characteristics: M1: 16 K words, 50 ns access time
M2: 1 M words, 400 ns access time
Assume eight word cache blocks and a set size of 256 word with set-associative mapping
Show the mapping between M2 and M1.
Calculate the effective memory access time with a catch bit ratio of h = 0.95.
(ii) What causes a processor pipeline to be underpipelined?
(iii) What is meant by a hierarchical bus system for multiprocessing system?

