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CS-12 Computer Architecture Dec-2002

Question Paper of CS-12 Computer Architecture Dec-2002 Ql(i) The SPARC architecture can be implemented with two to eight register windows for a total of 40 to 130 GPRs (General Purposed Registers) in the integer unit. Explain how the following designs. (a) Use 10 GPRs to construct two windows. (b) Use 72 registers (GPRs) to construct four windows. (c) In what sense is the SPARC considered a scalable architecture? (d) Explain how to use the overlapped windows for parameter passing between the calling procedure and the called procedure. Ql(ii) Answer the following question: (a) Comment on the advantages in using SIMD computers

CS -12 Computer Architecture June-2003

Question Paper of CS -12 Computer Architecture June-2003 Q.1(i) The SPARC architecture can be implemented with two to eight registe windows, for a total 40 to 132 General Purpose Registers in the intege unit. Explain how general purpose Registers (GPRs) are organized ini overlapping windows in each of the following designs: a) Use 40 GPRs to construct two windows. b) Use 72 G PRs to construct 4 windows. c) In what sense is the SPARC

CS -12 Computer Architecture June -2001

h1>Question Paper of CS -12 Computer Architecture June -2001 Q.I (i) Consider a cache (M(1) and memory (M2) hierarchy with the following characteristics: M1,: 16 K words, 50 ns access time M2: 1 M words, 400 ns access time Assume 8 words cache blocks and a set size of 256 words with set associative mapping. (a) Show the mapping between M2 and M1,. (b) Calculate the effective memory access time with a cache hit ratio of h = 0.95. a) Number of Blocks per set 256 /8 =32 blocks

CS -12 Computer Architecture Dec-2004

Question Paper of CS -12 Computer Architecture Dec-2004 Q.I (a) What is mean by inclusion, coherence, and locality in a memory hierarchy? Explain through diagram and examples. Q.I (b) What is meant by superscalar processor? Explain the concept of pipelining in superscalar processors with diagram. : Q.I (c) Shnv the pipelined execution of successive instructions in two unierpipelined cases and explain each case. Q-l (d) Derive the speedup execution for S(m, 1) to compare the relative performance of a superscalar processor with that

CS -12 Computer Architecture Dec-2003

Question Paper of CS -12 Computer Architecture Dec-2003 Q.I (a) Analyze the data dependence among the following statements in a given program fragment Load R1, M (100) /R1, { - M (100)/ Load R2, M (104) /!R2 { - M(104)/ Multi R1, R2