CS -12 Computer Architecture June -2001
h1>Question Paper of CS -12 Computer Architecture June -2001
Q.I (i) Consider a cache (M(1) and memory (M2) hierarchy with the following characteristics: M1,: 16 K words, 50 ns access time
M2: 1 M words, 400 ns access time
Assume 8 words cache blocks and a set size of 256 words with set associative mapping.
(a) Show the mapping between M2 and M1,.
(b) Calculate the effective memory access time with a cache hit ratio of h = 0.95.
a) Number of Blocks per set
256 /8 =32 blocks
Cache has
16k /256= 214 / 28
= 26
= 64 sets
No. of Blocks in memory
=1MB/8
_ 1024x1024 / 8
__1048576 / 8
= 131072
Image no.1
b)Teff = h1.t1.+(1-h)t2
= .95t1,=(l-.95)t2
=.95x50+ .05x400
= 47.5+20
= 67.5 n.sec.
(ii) Answer the following questions with reference to processors and memory hierarchy: (a) Explain the relationship between the integer unit and the floating point unit in most RISC processors with scalar or Superscalar organization.
(b) Explain the difference between superscalar and VL1W architectures in terms of H/W and SAW requirements-
© What are the design tradeoffs between a large register file and a large D-cache?
(iii) Define five important characteristics of parallel algorithms, which are machine implemental.
