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CS -12 Computer Architecture June -2001

h1>Question Paper of CS -12 Computer Architecture June -2001 Q.I (i) Consider a cache (M(1) and memory (M2) hierarchy with the following characteristics: M1,: 16 K words, 50 ns access time M2: 1 M words, 400 ns access time Assume 8 words cache blocks and a set size of 256 words with set associative mapping. (a) Show the mapping between M2 and M1,. (b) Calculate the effective memory access time with a cache hit ratio of h = 0.95. a) Number of Blocks per set 256 /8 =32 blocks

CS -12 Computer Architecture Dec -2001

Question Paper of CS -12 Computer Architecture Dec -2001 Q.I (i) What are the design parameters for pipeline processors? Discuss them briefly with examples. (ii) Discuss the structure of super scalar pipelines and the factors causing pipeline stalling. (iii) Consider the execution of an object code with 2,00,000 instructions on a 40 MHz processor. The program consists of four major types of instructions. The instruction mix and the number of cycles (CPI) needed for each instruction type are given below based on the result of a program trace experiment: Instruction type

CS -12 Computer Architecture June-2003

Question Paper of CS -12 Computer Architecture June-2003 Q.1(i) The SPARC architecture can be implemented with two to eight registe windows, for a total 40 to 132 General Purpose Registers in the intege unit. Explain how general purpose Registers (GPRs) are organized ini overlapping windows in each of the following designs: a) Use 40 GPRs to construct two windows. b) Use 72 G PRs to construct 4 windows. c) In what sense is the SPARC

CS -12 Computer Architecture Dec-2004

Question Paper of CS -12 Computer Architecture Dec-2004 Q.I (a) What is mean by inclusion, coherence, and locality in a memory hierarchy? Explain through diagram and examples. Q.I (b) What is meant by superscalar processor? Explain the concept of pipelining in superscalar processors with diagram. : Q.I (c) Shnv the pipelined execution of successive instructions in two unierpipelined cases and explain each case. Q-l (d) Derive the speedup execution for S(m, 1) to compare the relative performance of a superscalar processor with that

CS -12 Computer Architecture Dec-2003

Question Paper of CS -12 Computer Architecture Dec-2003 Q.I (a) Analyze the data dependence among the following statements in a given program fragment Load R1, M (100) /R1, { - M (100)/ Load R2, M (104) /!R2 { - M(104)/ Multi R1, R2