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Q.5 (a) Explain the following concept associated with multicomputer networks and message passing mechanisms: (i) Handshake protocol between wormhole routers
Q.5 (a) (ii) Asynchronous pipeling
Q.5 (b) Describe the following terms in the context of multiprocessor architecture: (i) Multiprocessing
Q.5 (b) (ii) Multitasking
Related Topics
Question Paper of CS -12 Computer Architecture June-2004
Q.I (a) Analyze the data depedendes among the following statements in a given program fragment:
S1,: Load R,, M(242) / R, r - M(242) /
S2: Load R,, M(240) / R, r- M(240) /
S3;MULTY R3,R1,R2/R3?(R1)x (R2) /
S4: ADDR...R1, R3/R1-(R1)x (R3) /
Ss: STORE M(240), R/M(248)?(R2) /
Draw a dependency graph to show all the three types of dependencies and explain them.
Q.I (b) Consider the main memory of a computer which has 128 blocks, where the size of each block is 16 words. The cache memory has 16-block-frames.
Sketch
Question Paper of CS -12 Computer Architecture June-2003
Q.1(i) The SPARC architecture can be implemented with two to eight registe windows, for a total 40 to 132 General Purpose Registers in the intege unit. Explain how general purpose Registers (GPRs) are organized ini overlapping windows in each of the following designs:
a) Use 40 GPRs to construct two windows.
b) Use 72 G PRs to construct 4 windows.
c) In what sense is the SPARC
h1>Question Paper of CS -12 Computer Architecture June -2001
Q.I (i) Consider a cache (M(1) and memory (M2) hierarchy with the following characteristics: M1,: 16 K words, 50 ns access time
M2: 1 M words, 400 ns access time
Assume 8 words cache blocks and a set size of 256 words with set associative mapping.
(a) Show the mapping between M2 and M1,.
(b) Calculate the effective memory access time with a cache hit ratio of h = 0.95.
a) Number of Blocks per set
256 /8 =32 blocks
Question Paper of CS -12 Computer Architecture Dec-2003
Q.I (a) Analyze the data dependence among the following statements in a given program fragment
Load R1, M (100) /R1, { - M (100)/
Load R2, M (104) /!R2 { - M(104)/
Multi R1, R2
Question Paper of CS-12 Computer Architecture June - 2002
Ql(i) Consider the execution of the following code segment.
Use Bernstein's condition to detect the maximum parallelism embedded in this code. Justify the portion that can be executed is parallel and the remaining portion that must be executed sequentially.
S1,:A = B + C
S2,: C = D + E
S3:F = G + E
S4: C = A + F
S5: M - G + G
S6:A = L + C
S7: A =