Question Paper of CS -12 Computer Architecture June-2003

Q.1(i) The SPARC architecture can be implemented with two to eight registe windows, for a total 40 to 132 General Purpose Registers in the intege unit. Explain how general purpose Registers (GPRs) are organized ini overlapping windows in each of the following designs:
a) Use 40 GPRs to construct two windows.
b) Use 72 G PRs to construct 4 windows.
c) In what sense is the SPARC considered a scalable architecture?

Q 1 (ii) Answer the following questions:
a) Plot the graph showing the speed-up factor and optimal numbers of pipeline stages for a linear pipeline unit. What ae the pros & cons?
b) What are the differences between string reduction and graph reduction
machines?
c) What are the problems encountered in scaling up a computer to massively parallel systems?
d) What are the cahracteristics of CISC and RISC architectures?

Question Paper of CS-12 Computer Architecture Dec-2002

Ql(i) The SPARC architecture can be implemented with two to eight register windows for a total of 40 to 130 GPRs (General Purposed Registers) in the integer unit. Explain how the following designs.
(a) Use 10 GPRs to construct two windows.
(b) Use 72 registers (GPRs) to construct four windows.
© In what sense is the SPARC considered a scalable architecture?
(d) Explain how to use the overlapped windows for parameter passing between the calling procedure and the called procedure.

Ql(ii) Answer the following question:
(a) Comment on the advantages in using SIMD computers as compared with the use of pipelined supercomputers for vector processing.
(b) Describe the language features of parallelism.
© Describe the basic metrics affecting the scalability of a computer system for a given application.
(d) Make diagrams of mesh and torus interconnection network and describe its characteristics.

Question Paper of CS-12 Computer Architecture June - 2002

Ql(i) Consider the execution of the following code segment.
Use Bernstein’s condition to detect the maximum parallelism embedded in this code. Justify the portion that can be executed is parallel and the remaining portion that must be executed sequentially.

(a) Distinguish between single threaded and multithreaded processor architecture.
(b) What difficulties will arise when a computer is scaled to become a-massively-parallel processing (MPP) system.
© Explain the differences between super scalar and very large instruction word (VLIW) architectures in terms of hardware and s/w requirements.
(d) Describe the advantages and shortcomings of daisy chaining scheme for bus arbitration in a multiprocessor system.
(e) Plot the graph showing the speedup factors and optimal number of pipeline stages for a linear pipeline unit. What are the pros and cons?

Question Paper of CS -12 Computer Architecture Dec -2001

Q.I (i) What are the design parameters for pipeline processors? Discuss them briefly with examples.
(ii) Discuss the structure of super scalar pipelines and the factors causing pipeline stalling.
(iii) Consider the execution of an object code with 2,00,000 instructions on a 40 MHz processor. The program consists of four major types of instructions. The instruction mix and the number of cycles (CPI) needed for each instruction type are given below based on the result of a program
trace experiment:

(a) Calculate the average CPI when the program is executed on a uni processor with the above trace results.
(b) Calculate the corresponding MIPS rate based on the CPI obtained in part (a).
(iv) What is the architectural distinction between RISC and CISC processors? Explain the concept of overlapping register windows in the SPARC architecture diagrammatically.

h1>Question Paper of CS -12 Computer Architecture June -2001

Q.I (i) Consider a cache (M(1) and memory (M2) hierarchy with the following characteristics: M1,: 16 K words, 50 ns access time
M2: 1 M words, 400 ns access time
Assume 8 words cache blocks and a set size of 256 words with set associative mapping.
(a) Show the mapping between M2 and M1,.

(b) Calculate the effective memory access time with a cache hit ratio of h = 0.95.

a) Number of Blocks per set
256 /8 =32 blocks
Cache has
16k /256= 214 / 28
= 26
= 64 sets

(ii) Answer the following questions with reference to processors and memory hierarchy: (a) Explain the relationship between the integer unit and the floating point unit in most RISC processors with scalar or Superscalar organization.
(b) Explain the difference between superscalar and VL1W architectures in terms of H/W and SAW requirements-
© What are the design tradeoffs between a large register file and a large D-cache?
(iii) Define five important characteristics of parallel algorithms, which are machine implemental.

Question Paper of CS -12 Computer Architecture Jan -2001

Q.I (i) The execution times (in seconds) of four programs on three computers are given below:
Execution Time (in seconds)

(ii) Answer the following questions:
(a) What causes a processor pipeline to be under pipelined?
(b) What are the factors limiting the degree of superscalar design?
© Compare the instruction set architecture in RISC and CISC processors in terms of instruction formats and addressing modes.
(d) Factors affecting cache hit ratio.

Question Paper of CS-12 Computer ArchitectureDec-2000

Q.I (i) Consider a catch (M1,) and memory (M2:) hierarchy with the following characteristics: M1: 16 K words, 50 ns access time
M2: 1 M words, 400 ns access time

Show the mapping between M2 and M1.
Calculate the effective memory access time with a catch bit ratio of h = 0.95.
(ii) What causes a processor pipeline to be underpipelined?
(iii) What is meant by a hierarchical bus system for multiprocessing system?

Question Paper of CS -12 Computer Architecture June -2000

Q.I A low level memory system has eight virtual pages on a disk to be mapped into 4 page frames in the main memory. A certain program generated the following page trace:

(ii) Perform a flow analysis of the assembly language obtained in part(i) to reveal all data dependence with a data dependence graph.

Question Paper of CS -12 Computer Architecture Dec -1999

Q.I (i) Draw a table showing performance factors versus system attributes and explain them.
(ii) A 50 MHz processor was used to execute a benchmark program with the following instruction and clock cycles counts.
Instruction type Instruction count Clock cycles count.
Integer Arithmetic 45000 1
Data transfer 32000 2
Floating point 15000 2
Control transfer 8000 2

(iii) What cause a processor pipeline to be underpipelined?
(iv) What are the factors limiting the degree of superscalar design?
(v) Illustrate a diagram showing asynchronous bus timing using a four edge handshaking (interlocking) with variable length signals for different speed devices.